library verilog;
use verilog.vl_types.all;
entity cmsdk_ahb_to_iop is
    port(
        HCLK            : in     vl_logic;
        HRESETn         : in     vl_logic;
        HSEL            : in     vl_logic;
        HREADY          : in     vl_logic;
        HTRANS          : in     vl_logic_vector(1 downto 0);
        HSIZE           : in     vl_logic_vector(2 downto 0);
        HWRITE          : in     vl_logic;
        HADDR           : in     vl_logic_vector(11 downto 0);
        HWDATA          : in     vl_logic_vector(31 downto 0);
        IORDATA         : in     vl_logic_vector(31 downto 0);
        HREADYOUT       : out    vl_logic;
        HRESP           : out    vl_logic;
        HRDATA          : out    vl_logic_vector(31 downto 0);
        IOSEL           : out    vl_logic;
        IOADDR          : out    vl_logic_vector(11 downto 0);
        IOWRITE         : out    vl_logic;
        IOSIZE          : out    vl_logic_vector(1 downto 0);
        IOTRANS         : out    vl_logic;
        IOWDATA         : out    vl_logic_vector(31 downto 0)
    );
end cmsdk_ahb_to_iop;
